Isolation of electrical signals in IC devices has been thoroughly addressed in the prior art, and a variety of approaches have developed. Complete isolation has been achieved in power ICs with dielectrically isolated structures. In this technique buried oxide tubs are formed around a silicon substrate region. The typical fabrication method is to etch deep trenches in a single crystal silicon substrate, oxidize the silicon in the trenches, and deposit a thick layer of polysilicon over the etched silicon surface. The polysilicon layer serves as the substrate or "handle" for the wafer during subsequent processing to form the integrated circuit. The bottom surface of the single crystal silicon wafer is polished away to reveal the oxide trenches thus leaving isolated islands of single crystal silicon in the polysilicon handle wafer. This approach is effective, but costly, and it consumes significant chip area. Junction isolation, i.e. guard rings, is the technique of choice in densely packed VLSI devices. Junction isolation is effective in blocking stray signals that propagate in the vicinity of the surface of the device. It is widely used in combination with the LOCOS process in commercial manufacture of LSI and VLSI MOS integrated circuits.
Another approach to dealing with interference in the substrate is to increase the resistivity of the substrate. Silicon on sapphire (SOS) and similar technologies have been developed which provide a high degree of isolation, but these types of wafers are difficult to process and are not economical for many applications.
In an effort to develop more robust isolation techniques, methods for forming surface regions of insulating material between devices but extending substantially into the substrate have been explored. The LOCOS process provides oxide regions that extend below the surface of the substrate. However, deeper oxide regions would be expected to be more effective, especially if they extend through, or largely through, the thickness of the active epitaxial device layer. In the early 1980s, techniques using deep trenches between circuit components were developed. V-groove trenches can be formed easily using crystallographic etching, but V-grooves were found to consume excessive chip area. The advent of effective anisotropic plasma etching techniques advanced this technology in that narrow trenches a few microns deep, with high aspect ratios, could be routinely formed. This allowed the chip area for the trenches to be reduced.
More recently, shallow trench isolation (STI) has been developed. Integrated circuits that operate with low voltages, i.e. 5 volts or less, and with shallow junctions, can be isolated effectively with relatively shallow trenches, i.e. less than a micron. In STI technology, the trench is backfilled with oxide and planarized using chemical-mechanical polishing (CMP). The result is a more planar structure than is typically obtained using LOCOS, and the deeper trench (as compared with LOCOS) provides superior latch up immunity. Also, by comparison with LOCOS, it has a much reduced "birds' beak" effect and thus theoretically provides a higher packing density for circuit elements on the chip.
The drawbacks in STI technology to date relate mostly to the planarizing process. Achieving acceptable planarization across the full diameter of a wafer using traditional etching processes has been largely unsuccessful. It has been proposed to use chemical-mechanical polishing (CMP) in which the wafer is polished using a mechanical polishing wheel and a slurry of chemical etchant. This technique successfully removes the unwanted oxide material but it also consumes the surface portions of the field oxide that are to remain as the isolating means, resulting in a "dishing" effect. Dishing destroys the planarity of the wafer and thus interferes with subsequent processing.
A proposal to overcome the dishing produced by the CMP step in STI technology is given in U.S. Pat. No. 5,362,669. The essential feature of this proposal is the use of a silicon nitride polish stop layer on the silicon active device regions prior to deposition of the fill oxide, and another silicon nitride layer over the fill oxide prior to the CMP step. If the level of the recess in the fill oxide matches the surface of the silicon substrate an essentially continuous nitride layer is available to stop, or sufficiently slow, the CMP when the surface is planar. This approach is conceptually sound, but in practice yields variable results which are due largely to the presence of the blanket layer of silicon nitride, and the excessive impedance of this layer during the CMP etch.